FIG. 25 is a circuit diagram showing a configuration of a conventional active matrix display device. As shown in this figure, the active matrix display device includes pixels (PXL) arranged in matrix on a horizontally oriented screen. Rows of the pixels are respectively connected to gate lines 201. The gate lines are connected to a vertical driver (vertical driving circuit) 202. On the other hand, columns of the pixels are respectively connected to data lines 203. Further, a signal line 204 is provided to feed a video signal (image signal) Vsig to the pixels. The signal line 4 is connected to the respective data lines 203 via sampling switches SW. The sampling switches operate to open and close sequentially in accordance with a control by a horizontal shift register (SR) via a horizontal driver 205.
The columns of the pixels of the horizontally oriented screen are divided into a predetermined section and extended sections. The predetermined section is assigned to a normal display. The extended sections each become a part of a wide display. The predetermined section contains pixels of the L+1th column to the Mth column. The extended sections contain pixels of the 1st column to the Lth column, and pixels of the M+1th to the Nth column. The horizontal shift register (SR) is divided into a predetermined-stage section (SRB) and extended-stage sections (SRA, SRC). The predetermined-stage section corresponds to the columns of the pixels in the predetermined section. The extended-stage sections (SRA, SRC) correspond to the columns of the pixels in the extended sections. In wide display, the predetermined-stage section (SRB) and the extended-stage sections (SRA, SRC) of the horizontal shift register are coupled serially to combine, and open and close all of the sampling switches sequentially. In normal display, the extended-stage sections (SRA, SRC) of the horizontal shift register are decoupled from the predetermined-stage section (SRB) so that only the sampling switches belonging to the predetermined section are opened and closed sequentially.
With this conventional arrangement, the horizontal shift register is divided into three sections: the extended front-stage section SRA; the predetermined in-between stage section SRB; and the extended rear-stage section SRC. A first gate circuit G0 is connected to an input terminal of the extended front-stage section SRA. A second gate circuit G1 is provided across an output terminal of the extended front-stage section SRA and an input terminal of the predetermined in-between stage section SRB. A third gate circuit G2 is provided across an output terminal of the predetermined in-between stage section SRB and an input terminal of the extended rear-stage section SRC. The gate circuits G0, G1, G2 are controlled to switch in accordance with control signals CTL0, CTL1, CTL2 to selectively combine and decouple the horizontal shift register. The first gate circuit G0, which is provided at a front end, is fed with a start signal ST for the shift register.
In the foregoing arrangement, the control signals CTL0, CTL1, CTL2 are all set to Low-level in wide display by an external control circuit. In some cases, the signals CTL0, CTL1, CTL2 may be fed via a shared control line. If CTL0 is set to Low-level in wide display, the start signal ST having been fed into the first gate circuit G0 is fed into the extended front-stage section SRA of the horizontal shift register. SRA transfers the start signal ST sequentially in synchronization with a predetermined clock signal to sequentially open, via the horizontal driver 205, the sampling switches SW that correspond to the pixels of the 1st column to the Lth column. Consequently, the video signal Vsig supplied from the signal line 204 is sampled by the data lines 203 that correspond to the pixels of the 1st column to the Lth column. Next, an output signal from the extended front-stage section SRA is fed into an input terminal of the predetermined in-between stage section SRB. SRB, in the same manner, transfers the signal to sequentially control the driving of the corresponding pixels of the L+1th column to the Mth column. The output signal of SRB is fed into the extended rear-stage section SRC. SRC, in the same manner, transfers the signal to sequentially control the driving of the corresponding pixels of the M+1th column to the Nth column. As a result of the foregoing operation, the pixels of the 1st column to the Nth column are all driven sequentially to show a wide display.
On the other hand, the start signal ST having been fed into the first gate circuit G0 is fed into the second gate circuit G1 in normal display. Thus, the extended front-stage section SRA of the horizontal shift register is decoupled. Therefore, the start signal ST is fed into the input terminal of the predetermined in-between stage section SRB. SRB transfers the start signal ST sequentially to drive the pixels of the L+1th column to the Mth column via the horizontal driver 205 and the switching devices SW. The output signal of the SRB cannot pass through the third gate circuit G2. Thus, the extended rear-stage section SRC is decoupled. Accordingly, the SRB transfers the signals only in normal display.
With the above-described conventional arrangement, the horizontal shift register constituted by flip-flops that are connected so as to form multi-stages is divided into the predetermined-stage section and the extended-stage sections. The predetermined-stage section corresponds to the normal display. The extended-stage sections correspond to the extended section in wide display. The predetermined-stage section and the extended-stage sections are connected via the gate circuits. In wide display, the predetermined-stage section and the extended-stage sections are connected serially via the gate circuits to combine. In normal display, the extended-stage sections are decoupled from the predetermined-stage section. Accordingly, it is possible to switch the wide display and the normal display with a simple arrangement in which the gate circuits are added to the horizontal shift register that is divided.    [Publication 1] Japanese Unexamined Patent Publication No. 20816/1995 (Tokukaihei 7-20816) (Publication Date: Jan. 24, 1995)